This invention is a circuit for resolving the phase difference between data that is locally generated and data that is remotely generated, and more specifically is a circuit for generating a number of clock phases and selecting the one which will process both local and remote data without showing a visible transition line.
In a scanning system, unless the data rate and start points of both locally and remotely generated video are synchronized to the scanner's speed, the resulting video could have a great deal of jitter and noise patterns. The severity of this jitter is judged by the overall print quality of the system. As tighter placements and quality prints are achievable from the rest of the system, the jitter contributions from the data and scanner speed mismatch become significant.
In most Raster Output Scanner (ROS) systems with polygon scanners, a phase locked loop (PLL) is used to synchronize the data pattern from scan to scan. This means that the clock that is utilized to clock in data will vary according to the motor speed and variations from facet to facet, depending on the scheme used.
To guarantee that the data sent by the host is properly received and processed to comply with the variation in the motor speed, the data from the host is read in by sending the clock generated by the PLL to clock-in data from the host. This approach guarantees that each pixel is plotted precisely in the same location from scan line to scan line as long as all the data is imported from a host.
In instances where document generation requires the mixing of internally generated and externally generated data, the existing approach will result in the processing of data with two clock phases, the phase differences of which are dependent on the cable length and the paths the clock had to go through before it is returned to the printer.
Unfortunately the cable length can vary from system configuration to system configuration and the clock delay path can vary from board to board, thereby excluding a possible approximation and predictive compensation for the phase delays.
In the specific application of this system, the white margin is generated using an internal clock, but the externally generated data is clocked in by the returning clock which takes over as the data arrives. The margin is programmable to compensate for ROS internal variables in terms of document placement. When this is done using the existing prior art approach, the result is a maximum uncertainty of .+-.1 pixel of jitter at the interface between internally and externally generated data. This, in turn, results in partially exposed pixels at the margins.
In a black and white printer, this is not significant. It may not be noticed if the first line of a page or the first pixel on every line is a shade of gray rather than a clear black or white pixel. However, in a tri-state printer using two colorants, where a line of partially exposed pixels may appear, for example, as a pink line on an otherwise black and white document, this is clearly visible as a system error. In fact, this color error may also happen in the middle of the page, where jitter will result in partially exposed, and therefore off-color, pixels. What is needed is a circuit that can resolve differences in clock phases and prevent clock jitter.